In the semiconductor industry, devices are fabricated by a number of processes to produce precisely-defined structures of an ever-decreasing size. Even the slightest structural defect can ruin a semiconductor device, and so to avoid losses of time and effort, detection of defects is critical before a defective device is mass-produced or further processes are performed on a defective wafer. Various inspection tools may be utilized, including those in which a view of a wafer (or other device or object) is compared to one or more reference views showing how the wafer should appear in a defect-free state. A reference image or images may be used for the comparison. For example, a reference image may depict or may be based at least in part on other portion(s) of the same wafer that (ideally speaking) contain the same structural features.
In some presently-existing inspection systems, wafers are inspected using die-to-die comparison or cell-to-cell comparison. For instance, an example of a component that may be included in a wafer is shown in FIG. 6. For instance, the component shown in FIG. 6 may comprise one of many dies in a wafer. The component may include areas that are best inspected using die-to-die inspection, such as the periphery area which may comprise, for example, logic components. Such areas may be checked for defects by comparison to one or more reference dies.
However, in other situations, cell-to-cell inspection may be desired. For example, the device shown in FIG. 6 includes a plurality of (ideally) identical memory cells of one or more types in the interior. For such cells, cell-to-cell inspection may be preferable since adjacent or nearby cells within the same die may be more similar than cells between adjacent dies. The similarities may be due to process conditions and/or the inspection tool itself. For instance, differences due to illumination, focus, or other optical irregularities may be less pronounced within a die as compared to between dies.
In some presently-existing inspection systems, cell-to-cell inspection is carried out using imaging and delay components. A first cell is imaged and then enters the delay component. A second cell is imaged and then compared to the image of the first cell in the delay component. A third cell is then imaged and compared to the second cell in the delay component, and so on. See, for example, U.S. Pat. No. 6,288,780. One disadvantage of such systems is that the delay component must be adjusted to account for different cell pitches (i.e. repetition sizes) in cases of multiple cell types. Furthermore, inspection of multiple cell pitches requires either duplicate inspection hardware or multiple inspection runs. Finally, the cells must be inspected in order—i.e. this means that, in some presently-existing systems, the wafer must be scanned in the same direction in which the cells repeat.